Towards Efficient Dynamic Run Time Reconfigurable Systems
By Ahmed Alwattar, PhD, 2009 - 2015
Abstract:
Reconfigurable Computing is a disruptive innovation technology intended to fill the gap between high performance ASICs and flexible software
general purpose processors.
Runtime partial reconfiguration is a recent method to update selectively the circuitry of an FPGA while still being active. This allows changing a
group of logic very quickly when the applications needs it.
However this comes at a price since the complexity of design increases with this flow. In this report we propose to implement an OS to manage
resources required in addition to improving the current flow.
The potential amount of speedup reconfigurable computing can reach depends on the application and amount of parallelism intrinsic to the target
application
In this thesis we propose to use image processing applications as a case study to demonstrate how dynamic partial reconfiguration can be
applied to achieve speedup, low power consumption and reduce cost.
