AN ARCHITECTURE EXPLORATION FRAMEWORK FOR THE IMPLEMENTATION OF EMBEDDED DSP APPLICATIONS
By Ahmed Elhossini, December 2009
Abstract:
Embedded systems are widely used today in different Digital Signal Processing (DSP)
applications that usually require high computation power and tight
constraints. Using SoC technology increases the challenges facing
a designer when choosing an appropriate design. A tool that helps
explore different architectures is required to design such an efficient
system. The tool should be able to explore different architectures
and evaluate them according to the given constraints. The design
space to be explored depends on the application domain and the
target platform.
This thesis proposes an efficient Particle Swarm Optimization (PSO)
technique that can handle multi-objective optimization problems.
It is based on the strength-Pareto approach originally used in
Evolutionary Algorithms (EA). The proposed modified particle-swarm
algorithm is used to build three hybrid EA-PSO
algorithms to solve different multi-objective optimization
problems. This algorithm and its hybrid forms are tested using
seven benchmarks from the literature and the results are compared
to the strength Pareto evolutionary algorithm (SPEA2) and a
competitive multi-objective PSO. Combining PSO and
evolutionary algorithms leads to superior hybrid algorithms that
outperform SPEA2, the competitive multi-objective PSO
(MO-PSO) and the proposed strength Pareto PSO based on different
metrics. Accordingly, an optimization engine is built using these meta-heuristics that can be used to solve
multi-objective optimization problems
in general and design exploration in particular.
The direction of the search process depends on the evaluation of each solution generated. In this thesis an
approach for performance evaluation of embedded systems is presented. Several cycle-accurate simulations are
performed for commercial embedded processors used in our study. The simulation results are used to build Artificial
Neural Network (ANN) models with accuracy up to 90% compared to cycle-accurate simulations with
a very significant time saving. These models are combined with an analytical model and static scheduler to increase the accuracy of the estimation
process. The optimization engine is integrated with the performance evaluation module to build an architecture exploration framework for embedded
DSP applications. The functionality of the framework is verified by using benchmarks from industry. The results show accuracy over 90%
comparing the proposed solutions to cycle-accurate simulation.
