A Handle-C Implementation of ANNs on Reconfigurable Platform
By Vijay Pandya, September 2005
Abstract:
Today Artificial Neural Networks (ANNs) are widely used in various
applications. The Back-Propagation algorithm for building an ANN
has been increasingly popular since its advent in the late 80's.
The regular structure and broad field of application of the BP
algorithm have drawn researchers' attention at attempting a
time-efficient implementation. General Purpose Processors(GPP) and
the ASICs have traditionally been the common computing platforms
to build an ANN based on the BP algorithm. However such computing
machines suffer from the constant need of establishing a trade-off
between flexibility and performance. In a last decade or so there
has been a significant progress in the development of special kind
of hardware, a reconfigurable platform based on Field Programmable
Array (FPGA). FPGAs are shown to exhibit excellent flexibility in
terms of reprogramming the same hardware and at the same time
achieving good performance by allowing parallel computation.
In this thesis various implementations of ANNs on hardware are
investigated. The research described in this thesis proposes three
parallel architectures and one fully parallel architecture to
realize the BP algorithm on FPGA. The proposed designs are coded
in Handel-C and verified for its functionality by synthesizing on
Virtex2000e FPGA chip. The validation of the designs are carried
out on two toy and one real world benchmarks. The partially
parallel architectures and the fully parallel architecture are
found to be 2.25 and 4 times faster than the software
implementation respectively. Also, all the parallel architectures
are found to exhibit high Weight Update per Second(WUPS).
