Low-Power Multi-Threshold CMOS Circuits Optimization and CAD Tool Design
By Wenxin Wang, May 2004
Abstract:
Over the last two decades, low-power design has become a concern in digital VLSI
design, especially for portable and high performance systems. As technology scales
into the Deep Sub-Micron (DSM) regime, standby subthreshold leakage power increases
exponentially with the reduction of the threshold voltage. Therefore, effective
leakage
minimization techniques are becoming a necessity. Multi-Threshold CMOS (MTCMOS) has
emerged as an effective circuit-level technique that attains a high performance,
while standby subthreshold leakage is minimized by cutting off the power of the
inactive blocks by sleep transistors. This research presents several techniques to
solve the leakage power problem in the form of Genetic Algorithms, Set-Covering and
Set Partitioning. In addition, an automatic MTCMOS design environment is devised and
integrated into the Canadian Microelectronics Corporation (CMC) digital ASIC design
flow.
