Area/Congestion-Driven Placement for VLSI Circuit Layout
By Zhen Yang, July 2003
Abstract:
A VLSI chip can today contain millions of transistors and is expected to
contain more than 1 billion transistors in the next decade.
In order to handle this rapid growth in integration technology,
the design procedure is therefore divided into a sequence of design
steps. Circuit layout is the design step in which a physical
realization of a circuit is obtained from its functional description.
Circuit placement is one of the key subproblems of the physical design
automation which involves finding the best position for all elements of
the circuit while minimizing the total estimated interconnecting wire length.
In this research, several global placement algorithms are constructed
and compared. Both flat and hierarchical approaches are implemented to find
the effectiveness of these approaches. Experiments conducted indicate that
the Attractor-Repeller Placer (ARP) method produces the best results and a
hierarchical approach can reduce the computation time of ARP by almost 85\%.
