ENG 2410: Digital Design

School of Engineering , University of Guelph
Fall 2024

Handout (Course Outline)

UOG Online Handout (Course Outline)

1st Meeting (PDF Version)

1st Meeting (PPT Version)

Course Instructor:

Prof. Shawki Areibi
Office: 2335, ext. 53819
Email: sareibi@uoguelph.ca
Web site: https://sareibi.uoguelph.ca/
Office Hours: Thursday 2:00 PM - 3:00 PM

Lab Instructor/Coordinator:

Haleh Vahedi
RICH Building, Room 1509, ext. 54741
Email: hvahedi@uoguelph.ca

Teaching Assistants:

TA #1: Erich MacLean
Office Hours: Monday 1:00 PM - 2:00 PM
Thornbrough Building, ext. NA
Email: emacle05@uoguelph.ca
TA #2: Yahuza Bello
Office Hours: Tuesday 4:00 PM - 5:00 PM
Thornbrough Building, ext. NA
Email: ybello@uoguelph.ca
TA #3: Jeny Patel
Office Hours: Wednesday 3:00 PM - 4:00 PM
Thornbrough Building, ext. NA
Email: jenyhare@uoguelph.ca
TA #4: Wissam Botros
Office Hours: Thursday 1:00 PM - 2:00 PM
Thornbrough Building, ext. NA
Email: wbotros@uoguelph.ca
TA #5: Hassan Saeed
Office Hours: None
Thornbrough Building, ext. NA
Email: hsaeed02@uoguelph.ca

Schedule:

Lectures (Class Times):(ALEX 100)

Tue & Thur 16:00 PM - 17:20 PM

Tutorials:

T01: Tuesday 13:30 PM - 14:20 PM (MINS 017)

T02: Tuesday 14:30 PM - 15:20 PM (MCKN 233)

T03: Wednesday 16:30 PM - 17:20 PM (MCKN 233)

T04: Thursday 14:30 PM - 15:20 PM (MINS 017)

Lab times:(As Indicated Below)

L01: (Monday) (9:30 AM - 11:20 AM) RICH 1532

L02: (Tuesday) (8:30 AM - 10:20 AM) RICH 1532

L03: (Thursday) (8:30 AM - 10:20 AM) RICH 1532

L04: (Friday) (9:30 AM - 11:20 AM) RICH 1532

Course Description:

This course is an introductory course in digital logic design, which is a basic course in most electrical and computer engineering progams.

Course Objective:

The main goals of the course are (1) to teach students the fundamental concepts in classical manual digital design and (2) to illustrate clearly the way in which digital circuits are designed today, using CAD tools.

Course Text:

D. Roth Jr. and L. Kinney, Fundamentals of Logic Design, Enhanced 7th Edition , Cengage, 2021.
Link to Web Site

Reference:

Morris Mano and C. Kime, Logic And Computer Design Fundamentals, Prentice Hall, 2013.
VHDL Tutorial by Shawki Areibi.
Tutorial On Using Xilinix Foundation Design Tools.
Fundamentals of Digital Logic with VHDL Design by Brown and Vranesic.

Evaluation:

Assignments:	(10 Assignments)	5%
Labs:	(7 Lab Components)	15%
Midterm Exam:	Week #7, Saturday October 26th, 2024, at 3:00 PM (Location: RICH 2520)	30%
Final Exam:	Week #13, Dec., 2024, Time: TBA, Location: TBA	50%

Safety:

To ensure your safety and the safety of others, please abide by the lab safety regulations. The lab coordinator will explain them to you during your first lab session. The following are some guidelines:

1. Do not wire up circuits or make any alterations to existing circuits while the power is on

2. Do not turn on any power until the circuit has been checked by an instructor or lab coordinator.

3. Do not touch any part of a circuit while power is connected to the circuit

4. Hit the emergency button if you notice the slightest hint of trouble in the lab.

Academic Misconduct:

Please refer to the regulations outlined in the student handbook regarding academic misconduct. The policy for this course is zero tolerancy for any form of academic misconduct. Further, late assignments and labs will not be graded.

Tentative Schedule:

Week	Topics
1	Introduction to Digital Design
2-3	Combinational Logic Circuits & Design
4	Combinational Logic Design Examples
5	Sequential Circuits
6	Cont .. Sequential Circuits
7	Sequential Circuit Design Examples
8	Registers and Counters
9	Memory & Programmable Logic Design
10	Register Transfers and Datapaths
11	Arithmetic Circuits
12	Algorithmic State Machines