The configurability of fine-grained reconfigurable logic devices allows designers
to specialize their hardware down to the bit level, meaning that, if an application
requires 7-or 17-bit arithmetic for an operation, the hardware can directly accommodate
what is needed. The configurability makes devices, like FPGAs, suitable to implement
a large variety of functions directly.
This configurability comes at a significant cost in terms of circuit area, power, and
speed. Every level of configurability requires more multiplexing, buffering, routing,
and/or
memory, thus, requiring more transistors and their interconnection.
In recognizing these costs, many researchers have studied how to use arrays of more
coarse grained reconfigurable operators as the basis for reconfigurable computing
machines.
You are required first to introduce the concept of Course Grained Reconfigurable Arrays
and describe just a few notable research architectures.
- Coarse Grained Reconfigurable Architectures (PDF)
- Coarse Grained Reconfigurable Systems (PDF)
- Evaluation Strategies for Coarse Grained Reconfigurable Architectures (PDF)
- MorphoSys: A Coarse Grain Reconfigurable Architecture for Multimedia Applications (PDF)
This page is maintained by Shawki Areibi, sareibi@uoguelph.ca
Last modified April 2008