Guelph University
School of Engineering
ENG6530: Reconfigurable Computing Systems

Xilinx ISE:

Design Entry Using: Schematic Capture of Half Adder using Digilent NEXYS3 Board (By SOE)

Behaviour Simulation of Half Adder using Digilent NEXYS3 Board (By SOE)

Design Entry Using: Schematic Capture of Full Adder using Digilent NEXYS3 Board (By SOE)

Design Entry Using: VHDL of Full Adder usig Digilent NEXYS3 Board (By SOE)

Design Entry Based on VHDL + Schematic Capture using Digilent NEXYS3 Board (By SOE)

Tutorial on Modelling State Machines