Guelph University
School of Engineering
ENG6530: Reconfigurable Computing Systems

Xilinx Vivado HLS CAD Flow:


Xilinx HLS Workshop (Labs):
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Lab #1 Tutorial, Matrix Multiply (Vivado HLS Design Flow Xilinx Lab Handout)
Lab #1, Matrix Multiply Resources
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Lab #2 Tutorial, RGBYUV (Improving Performance Xilinx Lab Handout)
Lab #2, RGBYUV Filter Resources
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Lab #3 Tutorial, DCT (Improving Area and Resource Utilization Xilinx Lab Handout)
Lab #3, DCT Resources
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Lab #4 Tutorial, FIR Filter (Creating a Processor System Xilinx Lab Handout)
Lab #4, FIR Resources

Resources online:
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Getting Started with Vivado HLS (YouTube)
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Xilinx VIVADO Video Tutorials (All Video Clips for Vivado)
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Xilinx VIVADO (2015.4) High Level Synthesis User Guide
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Xilinx VIVADO (2012.2) High Level Synthesis (Tutorial)
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Xilinx VIVADO (2013.2) High Level Synthesis (Tutorial)
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Xilinx VIVADO (2013.2) High Level Synthesis (PPT Tutorial)
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Xilinx VIVADO (2016.2) High Level Synthesis (Tutorial)
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Xilinx VIVADO Design Suite (User Guide)

AVNET ZedBoard Information:
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ZedBoard Bood Guide and JTAG Configuration
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ZedBoard User Guide
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ZedBoard Getting Started Guide

This page is maintained by Shawki Areibi, sareibi@uoguelph.ca
Last modified Sept. 2023